1. Field of the Invention
The invention relates generally to a method of manufacturing a high-voltage device and, more particularly, the invention relates to a method of manufacturing a high-voltage device, wherein a junction profile inhibits reduction of the intensity of an electric field, thereby securing breakdown voltage margin.
2. Discussion of Related Art
In a NAND flash device, a high bias voltage is used upon program/erase. To apply the high bias voltage to a cell, a high voltage transistor must be disposed at the end of word lines and bit lines so that a high voltage is smoothly applied thereto. If a voltage drop occurs when a voltage is transferred to the cell in the high voltage transistor, program/erase fail may be caused due to speed delay.
In the high-voltage device of 90 nm technology NAND flash that is now mass produced, the junction profile is somewhat abrupt and it leads to a situation where the junction breakdown voltage does not fulfill EDR (Electrical Design Rule) specifications (about 90%; refer to “A” in FIG. 3).